VLSI: Latest VLSI Projects based on Spartan 6 (commercial) XILINX Board

Do you know what a Spartan 6 (commercial) XILINX Board is? If not, read on.

Spartan-6 devices are the most cost-optimized FPGAs that offer industry-leading connectivity features such as high logic-to-pin ratios, small form-factor packaging, MicroBlaze™ soft processor, and a diverse number of supported I/O protocols.

Okay, so what is an FPGA?

An FPGA is a Field Programmable Gate Array. It is a type of device that is widely used in electronic circuits. FPGAs are semiconductor devices which contain programmable logic blocks and interconnection circuits. It can be programmed or reprogrammed to the required functionality after manufacturing so it is also called as Reconfigurable Hardware. Digilent Atlys FPGA Board is an commercial FPGA Board capable of doing real time video processing, image processing with the powerful DSP Processor.

What are the latest Projects based on Spartan 6 (commercial) XILINX Board, and where can you learn them?

The following shows a list of Projects based on Spartan 6 (xc6lx45) XILINX Board.

Sl. No.	Advanced VLSI Project Lists	Publications	Year
1	Design of modified Vedic multiplier and FPGA implementation in multilevel 2D-DWT for image processing applications	IEEE	2019
2	ADPLL Design and implementation on FPGA	IEEE	2019
3	Design and synthesis of reversible Arithmetic Logic Unit	IEEE	2018
4	Design of ALU using reversible logic based low power Vedic multiplier	IJSER	2019
5	Design and implementation of high performance Master/Slave memory controller bus architecture	IEEE	2017
6	Flexible DSP accelerator architecture exploiting carry save arithmetic	IEEE	2016
7	FPGA based real time citrus classification system	IEEE	2019
8	Simple hybrid scaling free CORDIC solution for FPGAs	Hindwai	2019
9	A modified CORDIC FPGA implementation for wave generation	Springer	2019
10	Redesigned scale free CORDIC algorithm base FPGA implementation of window function to minimize area and latency	Hindwai	2018
11	Leading one detection hyperbolic CORDIC with enhanced range of convergence	Springer	2018
12	An improved direct digital synthesizer using hybrid wave pipelining and CORDIC algorithm	Elsevier	2018
13	Reduced memory and low power architecture for CORDIC based FFT processors	Springer	2019
14	High performance hardware architectures for multi-level lifting based DWT	Springer	2018
15	Design of Sobel operator using Field Programmable Gate Arrays	IEEE	2019
16	A novel real time resource efficient implementation of Sobel operator based edge detection on FPGA	Taylor and Francis	2019
17	Novel shared multiplier scheduling scheme for area efficient FFT/IFFT processor	IEEE	2018
18	An efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT	IEEE	2018
19	Reconfigurable FIR filter using distributed arithmetic on FPGAs	IEEE	2017
20	An efficient VLSI architecture of a reconfigurable pulse shaping interpolation filter for multimodal DUC	IEEE	2018
21	Image and video processing with FPGA support used for biometric as well as other applications	Facta Universities	2019
22	A distributed Canny Edge detection: Algorithm and FPGA implementation	IEEE	2018
23	Super resolution image reconstruction using wavelet based patch and DWT	Springer	2018
24	A memory efficient scalable architecture for lifting based DWT	IEEE	2018
25	Memory efficient high speed convolution based generic structure for multilevel 2D-DWT	IEEE	2018
26	A novel local pattern descriptor-local pattern in high order derivative space for face recognition	IEEE	2018
27	An iterative logarithmic multiplier	Elsevier	2019
28	Detecting moving object using background subtraction algorithm in FPGA	IEEE	2019
29	Performance analysis of spatial color information for object detection using background subtraction	Elsevier	2018
30	A hierarchical model incorporating segmented regions and pixel descriptors for video background subtraction	IEEE	2019
31	Background subtraction for dynamic texture scenes using fuzzy color histograms	IEEE	2017
32	Moving object detection for video surveillance	Hindwai	2018
33	Area efficient VLSI implementation for parallel linear phase FIR digital filters of odd length based on fast FIR algorithm	IEEE	2019
34	Pipelined radix-2^K feed-forward FFT architecture	IEEE	2019
35	A real time motion feature extraction VLSI employing digital pixel sensor based parallel architecture	IEEE	2019
36	Optimized reversible Vedic multiplier for high speed low power operation	IEEE	2019
37	Design of dedicated reversible quantum circuitry for square computation	IEEE	2018
38	Ultra area efficient reversible multiplier	Elsevier	2018
39	K-algorithm: An improved Booth’s recoding for optimal fault tolerant reversible multiplier	IEEE	2017
40	Reversible watermarking based on sorting prediction scheme	IEEE	2018
41	A FPGA implementation of data hiding using LAS matching method	IJRET	2019
42	FPGA implementation for image steganography: A retrospective	IJEDR	2019
43	Enhancing security using video steganography and watermarking	AIVP	2019
44	Design approach for fault recoverable ALU with improved fault tolerance	VLSICS	2018
45	A watermarking algorithm based on chirp z_transform, discrete wavelet transform and singular value decomposition	Springer	2019